AMD Zen 6: Chips and Cheese details wider decode, doubled VNNI units and the Zen 6c split

Chips and Cheese has published a detailed microarchitecture analysis of AMD's next-generation Zen 6 core family, based on measurements of the EPYC 9686F (Zen 6) and EPYC 9996 (Zen 6c). At a high level Zen 6 looks like an incremental refinement of Zen 5, but the site argues the rework runs deeper, comparing the scale of change to the jump AMD made from Zen 1 to Zen 2.

Branch prediction and front end

Zen 6 carries forward the direction predictor from Zen 5, which Chips and Cheese previously measured as the best of any core it has tested. Accuracy is essentially unchanged while the predictor gets faster, and the cost of being wrong has shrunk: past the point where the predictor is overwhelmed, per-branch time plateaus at roughly 3 to 3.5 nanoseconds on Zen 6 versus 3.5 to 4 nanoseconds on Zen 5. The core also sustains two branches per cycle inside the L1 instruction cache, dropping to one per cycle beyond it. Branch target buffer changes favor speed over capacity, according to the analysis.

The bigger front-end news is decode. Zen 5 introduced dual decode clusters, but a single thread could only effectively use one of them. On Zen 6 a single thread can use both clusters, which effectively widens decode bandwidth for single-threaded code.

Integer and vector throughput

The execution engine stays close to Zen 5's with a few deliberate changes. Zen 6 restores Zen 4's NOP pairing, retiring up to 16 NOPs per cycle, and sustains 5.96 64-bit adds per cycle against Zen 5's 5.25 with the same six ALUs.

One resource is trimmed: integer multiply units drop from three to two, and PDEP and PEXT throughput falls from three to two per cycle. Chips and Cheese relays AMD's view that Zen 5's third multiplier did not justify its area cost.

On the vector side the floating-point units are unchanged, still handling two 512-bit FADDs, FMULs or FMAs per cycle, but VNNI units double from two to four, lifting a 512-bit VNNI test from 1.99 to 3.88 instructions per cycle, with Zen 6c matching it. VNNI is used in the inner loops of quantized inference and in video codec filters. Vector load bandwidth improves as well: Zen 6 moves four 256-bit vector loads per cycle where Zen 5 managed two, matching the 128 bytes per cycle of its two 512-bit loads, which matters because most shipped vector code still targets AVX1/2.

Zen 6 and Zen 6c diverge

Until now, AMD's Classic and Dense cores were functionally identical inside the core, differing mainly in cores per chiplet and L3 size. That ends with Zen 6. The divergence sits between micro-op dispatch and the load queue, and Zen 6c comes out larger across the board: the reorder buffer grows from 576 to 640 entries, the integer register file from 288 to 352, the vector scheduler from 138 to 180, and the load queue from 280 to 330. Chips and Cheese reads this as specialization, with Zen 6 tuned for high clocks and Zen 6c given more capacity to ride out memory latency.

The chiplets differ too: 12-core CCDs with 48 MB of L3 for Zen 6, and 32-core CCDs with 128 MB for Zen 6c, both at 4 MB of L3 per core.

Memory behavior and estimated performance

L3 latency rises from about 47 cycles on Zen 5 to 55 on Zen 6 and 66 on Zen 6c, though Zen 6's higher clock keeps nanosecond latency nearly flat at 10.7 ns versus 10.3 ns on the Zen 5-based EPYC 9355P, while the larger Zen 6c complex lands at 16.4 ns. Zen 6 also fixes an L2 quirk where Zen 5 delivered only about 42 bytes per cycle; the read path now reliably supplies 64. Store-to-load forwarding is unchanged from Zen 5.

In estimated single-threaded SPEC CPU 2026 results, the EPYC 9686F roughly matches the Ryzen 9 9950X3D2 in integer rate and beats it in floating point despite the client chip's larger L3, leading by about 4% and 11% respectively at a matched 4.1 GHz. The Zen 6c-based EPYC 9996 roughly matches the previous-generation EPYC 9575F while running about 900 MHz slower, and it edges out NVIDIA's Vera in integer while leading it by roughly 20% in floating point. The 9686F finishes about 18% ahead of the 9996 across both suites, and top-down pipeline analysis shows the two parts behaving almost identically in core-bound tests, with the meaningful differences concentrated in memory-heavy workloads.

Why it matters

For developers, the analysis translates into concrete guidance. AVX2-era code gets more load bandwidth without recompilation, VNNI-heavy quantized inference and video filtering loops roughly double in per-cycle throughput, and branchy code pays less for each mispredict. The Zen 6 and Zen 6c split is the bigger story: for the first time, per-cycle behavior differs within a single AMD generation, so code sensitive to out-of-order window size or memory latency may perform differently on dense parts than on standard server chips, a distinction worth building into benchmarks and capacity planning.