DeepX tapes out DX-M2 with Samsung PIM, claiming 100B-parameter inference under 5 W

What DeepX announced

South Korean startup DeepX has taped out the DX-M2, its second-generation AI accelerator, and says the chip can run inference on models of up to 100 billion parameters while drawing less than 5 W. According to EE Times, which interviewed founder and CEO Lokwon Kim, the design gives DeepX access to custom processor-in-memory (PIM) technology from Samsung. The target is generative AI on robots, drones and other hardware with tight thermal and battery limits.

The company's first chip, the DX-M1, focuses on vision workloads and is already in mass production, with DeepX reporting more than 100 purchase orders from customers in drones, robotics, smart factories, surveillance, healthcare and IoT.

Inside the DX-M2

EE Times reports that the DX-M2 is built to serve models with 20 billion to 100 billion parameters — roughly 3 billion to 20 billion active parameters — at 10 to 30 tokens per second depending on the model, all within the same 5 W envelope as the M1.

Kim told EE Times that the biggest change is memory bandwidth, which has tripled from 50 GB/s to 150 GB/s. DeepX also says design improvements doubled the NPU's power efficiency and that moving to a 2-nm process node doubled it again, bringing the chip to 80 TOPS. The M2 supports large mixture-of-experts models along with newer techniques such as speculative decoding and TurboQuant.

The processor-in-memory angle

Much of LLM inference is bottlenecked by shuttling weights between memory and compute — particularly general matrix-vector multiplication (GEMV), which depends on random memory access. PIM attacks this by running those memory-bound operations inside the memory chip itself, raising effective bandwidth and cutting access latency. PIM is on track to become a JEDEC standard with LPDDR6, but DeepX says it has spent a year and a half working with Samsung Memory to integrate the DX-M2 with Samsung's LPDDR5x-PIM, and has already received samples for in-house testing.

DeepX's simulations indicate that offloading GEMV into the PIM memory yields 6.7 times the tokens per second on Llama 3.1-8B compared with the DX-M2 on its own. Kim described the combination as "close to optimal" and said the follow-on DX-M3 will adopt the official LPDDR6 PIM standard, where the company expects a theoretical 5× to 8× uplift.

Compiler work and the trade-offs

The gains do not come free. Kim noted that the 6.7× speed-up carries 2.7× higher overall power consumption, though DeepX believes it can deliver a 2× gain within the same power envelope as non-PIM operation. Supporting this mode also requires what Kim called "substantial manual effort" in the compiler: a prototype compiler currently runs against a simulation of the PIM-enabled memory, and hardware modules are being built so the toolchain can be validated on physical hardware.

Ecosystem and customers

Tim Park, DeepX's director of strategic marketing, told EE Times that robotics firms currently prototyping on Nvidia's Thor platform want more on-device compute at lower power, and that automotive customers are seeking a low-power chip to run in-vehicle agents. To ease migration from Nvidia's Isaac robotics stack, DeepX offers its own equivalent, Newton: customers change their API calls from Isaac to Newton and run the same pipeline, with 17 compatible libraries available. Kim claims a switch can take under a second and that customers get roughly 20 times longer battery life after moving off Nvidia hardware.

DeepX is also working with Taiwanese OEMs on AI PCs, with Samsung on a next-generation smart hub, and has joined the AWS IoT ecosystem to support remote model updates through Greengrass. Other collaborations include integrating Intel's OpenVINO with the DeepX SDK, talks with AMD about a robotics platform based on the Kria reference board, and engagement with the Raspberry Pi and Baidu PaddlePaddle ecosystems. Hyundai Motor Group's robotics lab already uses the DX-M1, and Kim said more than 10 leading Japanese companies are evaluating the chips as Japan emerges as a major market for humanoid robots.

Why it matters

Running a 100-billion-parameter model on under 5 W would be a step change for edge AI: that class of model generally requires datacenter-class hardware today, while edge devices handle far smaller networks. If DeepX's numbers hold up on physical silicon — and several, including the 6.7× PIM gain, come from simulation — robots, drones and vehicles could run large models locally, with immediate sensor access and no dependence on connectivity. The Samsung partnership also points to a broader shift: with PIM heading toward JEDEC standardization in LPDDR6, computing inside memory may move from a vendor-specific trick to a mainstream building block. And by offering a low-friction path off Nvidia's Isaac stack, DeepX is aiming squarely at the incumbent's lock-in in physical AI.