India's ₹1.27 lakh crore Semicon 2.0 targets 3nm chip technology within eight years

The announcement

India's Union Cabinet has approved Semicon 2.0, the second phase of the India Semiconductor Mission, with a fiscal outlay of ₹1,27,500 crore — about $15 billion. Speaking to India Today in late August 2026, IT Minister Ashwini Vaishnaw said the country intends to develop chip technology spanning 7nm down to 3nm over the next eight years, and that India "now has 40nm technology."

The second claim needs unpacking. According to a dev.to analysis of the announcement, the 40nm figure describes design capability and process know-how gained through partnerships and research, not wafers rolling out of an Indian fab. The 3nm statement is a roadmap commitment, not a production guarantee.

Where Indian manufacturing actually stands

India's only operational fab, the state-run Semi-Conductor Laboratory in Mohali, runs an 8-inch wafer line at roughly 180nm, per SCL — a facility geared toward strategic and space-grade parts, sitting around fifteen process generations behind the leading edge.

The India Semiconductor Mission frames a production-relevant node range of 28nm–110nm, and that band applies to the new fabs being built rather than current output. The first major commercial facility, Tata Electronics' fab with Taiwan's PSMC in Dholera, Gujarat, valued around ₹91,000 crore, remains under construction and is designed around mature nodes. The ISM timeline targets commissioning of the first new fab in 2028.

What the money actually funds

Semicon 2.0 is an ecosystem program rather than a straight fab subsidy. Per the India Semiconductor Mission, it spreads across six pillars: chip design (including a ₹1,000 crore Design Linked Incentive scheme), domestic manufacturing equipment and materials, new silicon and compound-semiconductor fabs (covered at 40% of capex for CMOS silicon, 35% for others), advanced packaging (35% of capex for advanced facilities, 25% for the rest), R&D aimed at moving beyond the 28–110nm band, and talent development.

The design leg already shows traction. Per a July 2025 government statement reported by PIB, 23 chip-design projects have been sanctioned under the DLI scheme with a combined outlay of ₹803.08 crore including EDA tools, and 72 startups plus 278 academic institutions have been given access to commercial EDA software. Roughly 70,000 students across 332 universities have been trained on chip-design tools.

Why 3nm in eight years is a stretch

Three structural problems stand between the roadmap and the fab floor.

First, manufacturing experience compounds slowly. TSMC, Samsung and Intel each needed decades of process-learning cycles to master successive nodes. Design IP can be licensed, but the accumulated yield knowledge inside a production team is not something a country can simply purchase.

Second, cost. A single leading-edge fab routinely runs into the tens of billions of dollars — comparable to Semicon 2.0's entire budget, which has to cover a full ecosystem rather than one advanced line.

Third, the input stack is missing. EUV lithography tools, ultra-pure chemicals and gases, and specialty materials all require domestic suppliers, which is exactly what the machines-and-materials pillar is meant to build.

The dev.to analysis sketches the plausible sequence: a mature-node fab running at volume in Dholera, then advanced packaging, then 28nm-class production, then faster node progress with partners — with the India–Japan deep-tech corridor flagged as one realistic route for climbing nodes.

Why it matters

Advanced nodes concentrate where performance-per-watt decides the outcome: AI accelerators, flagship smartphones, telecom infrastructure and defense electronics. India's sovereign AI ambitions currently run on silicon the country does not fabricate, and Semicon 2.0 is the state's attempt to close that gap.

The near-term, higher-confidence returns sit in design, packaging and materials — packaging incentives alone cover 25–35% of capex, and demand is global. Engineers and students should read the 332-university EDA push as the real short-term opportunity, since DLI backing means Indian design startups can genuinely reach tape-out. Anyone building products on the subcontinent, though, should plan around domestically made mature-node chips (power, sensors, automotive, IoT) arriving this decade, and treat Indian leading-edge silicon before roughly 2034 as an aspiration rather than a schedule.