Nvidia sets server-grade requirements to bring CUDA to RISC-V

At Hot Chips 2026, Nvidia laid out how it plans to bring CUDA to RISC-V processors, according to Chips and Cheese. CUDA has grown into the dominant platform for GPU computing, including machine learning, but it currently only runs alongside x86-64 and aarch64 host CPUs. Extending it to RISC-V would let systems built on the open instruction set architecture drive Nvidia GPUs — provided the hardware clears a fairly demanding bar.

What Nvidia is asking for

Nvidia's starting point is an RVA23 CPU plus adherence to RISC-V's server SoC and server platform specifications. Those documents already cover much of what Nvidia expects from a server-grade part: RAS (reliability, availability and serviceability) features, a specialized security processor and other baseline capabilities.

On top of the official specifications, Nvidia added requirements of its own, motivated by problems its software team hit while porting CUDA. The company wants to avoid a lowest-common-denominator situation in which it cannot rely on performance-enhancing extensions being present and would have to ship inefficient code as a result. Vector extensions are one example: predication support lets CUDA avoid branches.

ACPI was a bigger obstacle. Software uses ACPI to discover what hardware can do and to manage power, performance and thermals, and RISC-V hardware lacked it when the porting effort began. That gap has since closed: the UEFI Forum added RISC-V ACPI support in 2025, and the ratified RISC-V Boot and Runtime Services specification includes it.

Coherency and peer-to-peer PCIe

Nvidia also insists on PCIe cache coherency. Without it, DMA transfers can go wrong in both directions: the GPU's DMA engines may read stale data from DRAM while modified data still sits in CPU caches, and the CPU may read stale cached data after the GPU writes results back to memory. Working explicit cache invalidations into the CUDA stack would be difficult, and Nvidia treats coherency as table stakes for a server CPU. The RISC-V server SoC specification merely recommends it; Nvidia wants a guarantee.

Peer-to-peer PCIe communication is another requirement. Lacking it, buffers copied between two devices would have to detour through CPU memory, costing performance and adding synchronization complexity. Nvidia did not detail every requirement, noting only that it is targeting a certain performance level and that the whole list fits within two pages.

NVLink Fusion widens the scope

The talk also touched on requirements for NVLink Fusion, the program that lets other companies implement Nvidia's NVLink IP in their own chips and attach a custom CPU — potentially a RISC-V one — via NVLink C2C. Chips and Cheese points to Nvidia's GB10 as the model, where a MediaTek CPU die was linked to an Nvidia GPU. Fusion demands everything CUDA does, plus whatever is needed for software frameworks such as DOCA and NCCL, plus a close partnership with Nvidia on the order of MediaTek's collaboration.

Few systems will qualify today

As Chips and Cheese emphasizes, none of this means you can plug an Nvidia GPU into an existing RISC-V board and start running CUDA. The overwhelming majority of current RISC-V hardware falls short, and the author doubts any consumer RISC-V hardware will meet the requirements any time soon, with ACPI adoption a particular sticking point — even aarch64 ACPI support has been patchy despite years in the standards. Early CUDA-capable systems will almost certainly be servers. Nvidia is partnering with SiFive, which planned to demonstrate a system running CUDA at Hot Chips, with the example CPU specifications on Nvidia's slide suggesting a high-core-count server chip.

Why it matters

CUDA's reach underpins Nvidia's data center business, and the host CPU side of that ecosystem has so far been closed to anything outside x86-64 and aarch64. Formally defining what a RISC-V platform must provide to join it gives RISC-V vendors a concrete, Nvidia-endorsed target for server silicon, and the SiFive demo suggests the path is more than theoretical. The open questions are equally consequential: whether Nvidia's requirements stay strict, effectively limiting RISC-V to specialized enterprise designs, or relax over time so that smaller and hobbyist systems can participate too. Chips and Cheese hopes for the latter, arguing that missing vector extensions or PCIe coherency impose performance costs rather than hard blockers for many workloads, and that Nvidia will not actively block CUDA from running on unsupported hardware.