Open-source V100 SXM2 reference publishes pinouts and NVLink plans for multi-GPU boards

What the reference contains

An open-source hardware project has published a reference kit for NVIDIA's V100 SXM2 compute modules, comprising curated pin maps for the module's two 400-contact connectors, NVLink connection plans for two- and four-GPU systems, and connector-only KiCad starter projects. The repository, pigeon-labs-stack/v100-sxm2-reference on GitHub, surfaced on Hacker News and is positioned as the groundwork for a community-designed carrier board.

According to the project's GitHub page, the kit documents 800 canonical contacts: 400 on connector A, which carries PCIe, power and control signals, and 400 on connector B, which handles NVLink and management. Each contact is listed with its signal name, the evidence behind it, and notes on its electrical treatment.

Beyond the pin maps, the repository includes connection tables for two- and four-GPU NVLink topologies, specifying exact connector B pads, signal directions, lanes and polarity. The two-GPU arrangement covers six connection groups derived from documented pairing families, while the four-GPU plan follows a curated topology; both guides state their source evidence and remaining uncertainties.

Three editable KiCad starters are provided: one covering a single module's A and B connectors, plus two- and four-module versions with NVLink data wiring already connected. Every contact stays labelled, including unconnected clocks, power and control pins. The projects open in KiCad 10.0.7 or a compatible newer version, and the repository also ships complete schematic PDFs and a standalone workbook for reading without the CAD tool.

What it is not

The project is explicit about its limits, describing itself as a public reference pre-release rather than a hardware-qualified carrier board. The starters deliberately omit regulator, power-control and clock circuitry, and the NVLink schematics show data wiring only: each V100 still requires an external 156.25 MHz differential NVHS clock on connector B pads E20 and F20, with a separate 100 MHz PCIe clock on connector A pads E7 and F7. The connection plans are logical arrangements, not routed bridge schematics, and a raw PCB footprint is not included in this edition.

Curation on top of reverse engineering

The author states that the contribution so far is primarily curation — gathering public information, comparing sources, and reconciling conflicting connector orientations and signal names — while the original reverse-engineering work belongs to its authors, credited in the repository's attribution section. Corrections are invited, particularly ones backed by oriented drawings, continuity results or measured behaviour, and contributors are asked to distinguish confirmed observations from interpretations.

Original hardware design contributions are licensed under CERN-OHL-W-2.0, with documentation, diagrams and the workbook under CC BY-SA 4.0; both licences permit commercial reuse with attribution and applicable reciprocal sharing. The stated long-term goal is a reusable open-source board design, with routed boards, manufacturing outputs and hardware qualification listed as future work on the roadmap. Ongoing discussion is happening on the Level1Techs forums, where the effort is framed as designing an open-source budget 4x V100 SXM2 NVLink backplane.

Why it matters

SXM2 modules do not fit standard PCIe slots, so putting surplus V100 hardware to work requires a purpose-built carrier board that has historically existed only as proprietary datacenter equipment. By publishing evidence-tagged pinouts, vetted interconnect plans and ready-to-edit KiCad symbols, the project lowers the barrier for hobbyists and small labs to attempt multi-GPU builds with NVLink intact rather than falling back to PCIe-only connections.

The approach also models how community hardware documentation can be done responsibly: every claim carries its evidence, uncertainties are flagged, and the kit is clearly scoped as a reference rather than a finished product. Anyone building on it still faces the hard parts — power delivery, clocking, routing and qualification — but they no longer start from a blank schematic.