OpenAI's LLMs helped take the Jalapeño chip from concept to silicon in under 20 months

On 25 August, OpenAI fully unveiled Jalapeño, its first in-house AI accelerator, and a detailed IEEE Spectrum report shows the headline specs are only half the story. The chip delivers up to 13.4 petaflops of 4-bit compute and connects to 232 gigabytes of the most advanced memory available at 15.4 terabytes per second. OpenAI's benchmarks claim Jalapeño can cut end-to-end inference latency — prompt to last token — by up to 3.6 times versus Nvidia's GB300, a chip OpenAI still relies on, while consuming less power. Whether those gains hold once the chip enters widespread service in OpenAI's inference fleet remains to be seen.

The other half of the story is the design process itself, which OpenAI's own large language models helped accelerate at every stage.

A small team on a compressed schedule

Jalapeño went from first architecture concept to first silicon in under 20 months, with only nine months between the first register-transfer level (RTL) code and tape-out. The team behind it averaged fewer than 100 people, according to Richard Ho, OpenAI's vice president of hardware — a count spanning system design, software and supply chain roles, but not staff at partner Broadcom.

The Broadcom partnership split design from implementation. OpenAI owned the end-to-end system design, including the inference accelerator, the memory hierarchy and networking, while Broadcom handled physical design "from the gates onward," Ho told IEEE Spectrum.

Outside experts offered qualified praise. David Chin, co-founder of agentic chip-design startup Verkor.io, called the schedule credible but argued Broadcom's help was essential to the pace. Verkor co-founder Ravi Krishna deemed it a relatively impressive result and said a project started today with improved LLMs could move faster still. Andrew Kahng, a distinguished professor at the University of California, San Diego, called the timeline "likely best in class today."

Why LLMs fit the front end

Ankur Srivastava, who directs the semiconductor initiative at the University of Maryland, told IEEE Spectrum that automation in chip design is decades old. What distinguishes LLMs is their command of language and code, which makes them suited to tasks that still live in what he called the linguistic domain of the problem.

OpenAI's front-end workflow was built around Accelerated Hardware Synthesis (XLS), an open-source high-level synthesis toolchain originally developed at Google. Engineers write in DSLX, a Rust-inspired domain-specific language, or C++, and XLS converts the result into Verilog. "The AI was much better at software-looking things," Chris Leary, a member of OpenAI's technical staff who started XLS at Google, told IEEE Spectrum — and XLS in many ways looks like software. Kahng agreed that high-level synthesis is "more natural for the LLM to work with" and said the workflow "has legs" going forward.

Models tuning their own hardware

The AI assistance did not stop at tape-out. When the first chips returned from the foundry in May, the team pointed internal models at writing the software needed to run benchmarks such as SemiAnalysis's InferenceX. On DeepSeek's multi-head latent attention kernel benchmark, performance rose from 0.31 percent of the theoretical ceiling — the limit set by the chip's compute and memory bandwidth — to 88.94 percent in roughly 40 hours. Ho says the result is repeatable, and that OpenAI now bases its schedule assumptions on having this capability, shrinking the gap between first silicon and production ramp.

The models evolved alongside the project. Work began with o3-era systems, released publicly in April 2025, and ended with precursors to GPT-6 Astra, which reached the public on 3 September 2026. Leary says the newer models can work directly in Verilog without XLS's translation layer and are close to operating proprietary design tools on their own. Ho also confirmed the team used internal LLMs fine-tuned for chip design that are not publicly available, and said the lessons will feed future releases: "Astra and following models will be very good at chip design."

Backend work — routing interconnects, completing clock and power specifications, and preparing the design for the foundry — largely sat with Broadcom, though OpenAI physical-design engineers worked alongside them. Jalapeño is built for deployment in pods of 2,048 chips.

Why it matters

This is one of the most concrete public demonstrations yet of LLMs compressing a flagship silicon project: concept to first silicon in under 20 months with fewer than 100 engineers, and kernel bring-up measured in hours rather than weeks. If the approach scales, it shortens the feedback loop between frontier models and the accelerators that run them, letting AI labs iterate on hardware at something closer to software pace. It also turns chip-design skill into a feature of the models themselves, with OpenAI promising that capability will appear in commercial releases. The caveats are real — the benchmarks are OpenAI's own, fleet-level performance is unproven, and Broadcom carried the physical implementation — so the milestone is AI-assisted design rather than fully AI-designed silicon. Even so, the experts quoted by IEEE Spectrum expect these timelines to keep shrinking as the models improve.