Researchers publish bit-accurate models of AMD GPU matrix cores

Researchers have produced software models that reproduce, bit for bit, the output of the matrix multiplication units in three generations of AMD GPUs. According to the paper's abstract on arXiv (2609.14845), the models cover the CDNA 1, CDNA 2 and CDNA 3 architectures — corresponding to the MI100, MI210/MI250 and MI300A/MI300X accelerators — and were validated against real hardware with a suite of 10 million randomized input sets. The work surfaced on Hacker News's front page on 16 September 2026.

Standard floats do not apply

The matrix multipliers at the heart of modern GPU acceleration do not conform to IEEE 754, the floating-point standard that most software assumes. Their behavior varies not only between vendors but between generations of the same vendor's chips, the paper explains: the width of the accumulator, when rounding is applied, where normalization happens, how intermediate underflow and overflow are handled, and how subnormals and special values are treated all differ.

The consequence is that identical small matrix multiplications produce different results on different devices, and software alone cannot make them agree because the underlying implementation details are undocumented. That leaves developers unable to say whether a discrepancy reflects a genuine numerical property or an unadvertised hardware quirk.

Reverse-engineering the numerics

To characterize the units, the authors designed test vectors aimed at specific numerical features across all the input formats the hardware supports. The paper gives the derivation and reasoning for why each vector pins down a particular behavior purely from the outputs a device produces — a form of black-box probing that requires no access to internal design documents.

Those observations were then encoded in MATLAB-based models, one per architecture. Reaching bit-exact agreement took an iterative technique the team had developed previously: randomized testing, followed by refinement of the tests, repeated until the model matched the hardware on every case. The final check ran 10 million random input sets, with the models reproducing the silicon's outputs exactly each time.

A benchmark against NVIDIA

As a proof of concept, the authors ran the models in two demonstrative numerical applications, using them to quantify application-level accuracy differences between AMD's matrix cores and NVIDIA's tensor cores. The abstract does not specify which applications were used, but the exercise illustrates the kind of comparative research the models enable once exact hardware behavior can be simulated.

Version 1 of the paper was submitted to arXiv by Faizan Ahmad Khattak on 13 September 2026, with a revised version following on 15 September.

Why it matters

Bit-level reproducibility is a persistent pain point in GPU computing. Training and inference results can shift when workloads move between accelerators, regression tests become flaky, and mixed-precision AI pipelines are hard to audit when the arithmetic underneath is a black box. By turning undocumented matrix-core behavior into explicit, validated models, this work gives researchers and engineers a reference they can diff against, a tool for debugging cross-device discrepancies, and a way to study numerical accuracy without occupying scarce hardware. It also levels the field between vendors: claims about numerical quality can be measured rather than guessed, which is precisely what the AMD-versus-NVIDIA comparison in the paper begins to do.