vfmaddrnd231pd: Intel documented an FMA rounding instruction that never shipped

A phantom entry in the manual

A blog post by purplesyringa, which reached the Hacker News front page, walks through an odd corner of Intel's documentation: an x86 instruction called vfmaddrnd231pd that is described in detail in the Intel Software Development Manual but appears to have never existed in any shipping CPU.

According to the post, the 2024 edition of the SDM carries a full entry for the instruction, describing a fused multiply-add over packed double-precision values whose behaviour is steered by an immediate byte. That immediate, the manual says, packs several bit fields covering rounding mode, denormals-are-zero (DAZ), flush-to-zero (FTZ) and exception suppression. The "rnd" in the mnemonic is what sets it apart from the ordinary FMA family, whose members look like vfmadd231pd.

The capability it describes is genuinely desirable. Ordinary x86 floating-point code inherits its rounding mode from a global control setting, and rewriting that setting is comparatively slow. An instruction with per-use rounding baked into an immediate would avoid that cost. The author notes that because an FMA can stand in for plain addition, subtraction and multiplication, one such instruction would effectively give almost any floating-point arithmetic controllable rounding on hardware without AVX-512, which the post argues would make some rounding-dependent algorithms dramatically faster.

Every check comes back negative

The instruction fails every practical test the author applied:

• GNU assembler does not recognise the mnemonic.
• The intrinsics the manual names, _mm_fmaddround_pd and _mm256_fmaddround_pd, are missing not only from Clang but from Intel's own compiler, ICC.
• Building the encoding by hand from the manual's opcode entry, VEX.DDS.128.66.0F3A.W1 B8 /r /ib, runs into a stray "DDS" notation that appears nowhere else in the document. A Stack Overflow answer the author cites says DDS served only documentation purposes and was dropped from later SDM revisions.
• On a Haswell machine, which does implement the FMA set, executing the instruction raises #UD, the undefined-instruction exception.

Two further oddities stand out. The manual documents only this single pd/231 variant rather than the usual matrix of ps/pd/sd/ss operand widths combined with 132/213/231 operand orders that real FMA instructions have. And the entry disappears entirely from the 2026 edition of the SDM, despite being present in 2024.

What probably happened

The author rejects the idea of a simple typo, because the entry comes with dedicated tables and pseudocode that resemble no other instruction's write-up. The best explanation offered is that Intel planned a vfmaddrnd* family, ran into a problem late in development, stripped it from the silicon, but failed to clean the manual up for years afterwards. The author concedes there is no way to confirm this hypothesis and closes by asking anyone with contacts inside Intel for the real story.

Why it matters

For low-level developers, the SDM is normally treated as the definitive statement of what x86 silicon does. A multi-year ghost entry, complete with unique pseudocode, named intrinsics and an unusual encoding notation, shows that even that source can drift from what processors actually accept, and that documentation-derived behaviour still has to be validated against real hardware.

The story also highlights what was apparently lost. Per-instruction rounding without requiring AVX-512 would have been a meaningful capability for code whose correctness or speed depends on controlling rounding, particularly across the large installed base of machines that never gained AVX-512 support.

Finally, the silent removal between manual editions matters in itself. Without an accompanying note, a reader of the 2024 SDM has no way to know the instruction never shipped, and a reader of the 2026 edition has no way to know it was ever promised.